The 68020’s postindexed memory addressing mode can be expressed by the effective address ([64,A0],D3*2,24)
a. Both graphically and in words, demonstrate how this effective address is calculated.
b. What are the inner and outer displacements in this effective address?
c. What is index register scaling, and why is it implemented?
This is a memory indirect addressing mode. A table of pointers in memory is searched. The pointer is read and
used to access the operand. In this example, the first level pointer is given by [A0] + 64; that is the memory
location given by the contents of A0 plus 64 is accessed. At this location there is a pointer. This pointer is
accessed and used to locate a data structure in memory. The contents of register D3 are multiplied by 2 and 24
added to the result. This value is the offset from the start of this data structure (given by the memory pointer)
to the desired element. This CISC instruction requires three register reads, two memory accesses, a register
multiplication, and two additions: a lot of work for a single instruction. The equivalent ARM processor code
would be:
LDR r1,[A0,#64] ;get the pointer to the pointer in memory
LDR r1;[r1] ;now read the pointer from memory
ADD r1,r1,r3, lsl #1 ;add the register offset (r3 is d3)
ADD r1,r1,#24 ;add the literal offset
LDR r2,[r1] ;now get the target operand (r2 holds the operand)
Note that we’ve destroyed the original r1. The 68K code does not do that.
a. The following figure illustrates ([64,A0],D3*2,24)
b. The inner displacement is 64 (index into the table of pointers) and the outer displacement is 24 (index into
the selected data area).
c. The index register in this example is D3, which is added to the pointer accessed from memory. The index
register can be scaled by 1, 2, 4, or 8. This allows you to step over items that are 1, 2, 4, or 8 bytes wide. It
is useful in accessing arrays.
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