The circuit shown in Figure P15.41 represents a sample-and-hold circuit, such as might be used in a successive-approximation ADC. Assume that the NMOS is turned on when vG is high and off when vG is low. Explain the operation of the circuit.



Find:

Explain the operation of the circuit.


Analysis:
Op-amp #1 is an input buffer. The JFET behaves as a low-leakage diode which enables and disables the RC holding circuit, and op-amp #2 is a voltage-follower whose purpose is to isolate the circuit from the load.

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