Consider the same problem as question 54 except that the cache uses a writeback mode. On average 25% of cache lines are dirty (have been modified).
What will be an ideal response?
Consider all the possible outcomes of an access to memory/cache
Read hit: Zero bandwidth as the data is in cache and memory is not accessed
Read miss: 108 (bus frequency) × 0.05 (miss rate) × 0.70 (reads) × 16 × (1 reload + 0.25 writeback dirty line) =
7.00 × 107 B/s
Write hit: Zero (No write through – data stored in cache and dirty bit set)
Write miss: 108 (bus frequency) × 0.05 (miss rate) × 0.30 (writes) × 16 (1 reload + 0.25 writeback dirty line) =
3.00 × 107 B/s
Total bandwidth = (0.00 + 7.00 + 0.00 + 3.00) × 107 B/s = 10 × 107 Bytes/s or 25 M bus transactions/s
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