Suppose you execute LDR,r0=0x12345678 on an ARM machine followed by STR r0,[r1] where r1 = 0x1000. Now, suppose you do a byte read to the same address with LDRB r2,[r1]. What would the value be in r2 if (a) the ARM was big?endian configured and (b) it was little?endian configured?
What will be an ideal response?
This question demonstrates the perils of endianism when you work with both bytes and words. In a big?endian world, the byte read would be 12, and in a little?endian world 78 would be read.
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Suppose that transactions T1 and T2 can be decomposed into the subtransactions T1 : T1,1, T1,2 and T2 : T2,1, T2,2 such that each subtransaction individually maintains the consistency constraints of the database. Instead of guaranteeing that all schedules involving T1 and T2 are serializable, suppose that a concurrency control guarantees that all subtransactions are always executed serializably.
a. Will T1 always be serializable with T2? Explain. b. Will integrity constraints be maintained by all possible schedules? c. What possible problems might arise if the concurrency control schedules transactions in this way?
The following catch statement
catch(...) a. is illegal b. catches only numeric exceptions c. catches all exceptions d. should be the first catch block if multiple catch statements are present
When a higher-priority thread enters the ready state, the operating system generally preempts the currently running thread (an operation known as preemptive scheduling). Depending on the operating system, a steady influx of higher-priority threads could postpone—possibly indefinitely—the execution of lower-priority threads. such indefinite postponement is sometimes referred to more colorfully as________.
a. fasting b. famine c. starvation d. malnourishment
How often does Windows 7/Vista automatically defragment a hard drive?
A. once a week B. once a day C. once a month D. once an hour