A RISC processor executes the following code. There are no data dependencies.
ADD r0,r1,r2
ADD r3,r4,r5
ADD r6,r7,r8
ADD r9,r10,r11
ADD r12,r13,r14
ADD r15,r16,r17
a. Assuming a 4?stage pipeline fetch, operand fetch, execute, write, what registers are being read during the 6th
clock cycle and what register is being written?
b. Assuming a 5?stage pipeline fetch, operand fetch, execute, write, store, what registers are being read during
the 6th clock cycle and what register is being written?
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