In this case we have to consider pairs of memory accesses across two trips round the loop. On the first trip, a memory access takes place, a miss occurs and memory is accessed and L2 updated with the second line. The access time is as before, 44 cycles. On the second trip, an access to the array does not miss and the access time for the loop is 6 (L2) + 2 + 2 = 10 cycles. The average memory time per loop is ½ (44 + 10) = 27 cycles.
What will be an ideal response?
The total cache is 128K and this is divided between 8 direct?mapped caches. Consequently, each cache has a
capacity of 128K/8 = 16 KB.
The cache is divided into 128 sets, 27. A line consists of 16 words and a word is 8 bytes (i.e., 16 × 8 = 128
bytes/line).
It takes 7 bits to specify a byte in a line (the index) and 7 bits to specify a set. This leaves 64 ? (7 + 7)
= 64 ? 14 = 50 bits for the tag.
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What will be an ideal response?