What is the effect of LDR r0,[r5,r6, LSL r2]?
What will be an ideal response?
This is load register instruction using address register indirect addressing. The 32?bit value at the effective address
is loaded into register r0. The effective address is calculated from ‘r5,r6, LSL r2’. First, register r6 is shifted left
(multiplied by 2) by the value in register r2. Then, this value is added to register r5 to give the value of the
effective address. For example, if 
r6 = 3, and r2 = 4, then r6 becomes 3 × 2 × 2 × 2 × 2 = 48 = 
The effective address of the operand is 
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