A 64?bit processor has an 8 MB 4?way set associative cache with 32?byte lines. How is the address arranged in terms of set, line, and offset bits?
What will be an ideal response?
If the cache is 4?way set associative, it means that there are four 2 MB direct?mapped caches. Each cache is spanned by address lines A00 to A20. Since this is a 64?bit processor, the words are 64/8 = 8 bytes. Address lines A00 to A02 selects a byte of a word and address lines A03 and A04 select one of 32/8 = 4 words per line. The cache has 2 MB/32 = 221/25 = 216 = 64 K lines. The line address is provided by 16 bits A05 to A20. This leaves address lines A21 to A31 to select a set (or A21 to A63 if this is a 64?bit address as a 64?bit processor would imply).
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This chapter has describes and applied the following patterns:
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Indicate whether the statement is true or false