The circuit below consists of four JK flip?flops. Inputs J and K are not shown because it is assumed that they are both permanently connected to a logical 1. These JK flip?flops are positive edge triggered (i.e., they change state on the rising edge of the clock). Note that these flip?flops have a CLR (clear) input that sets Q to 1 when CLR = 1. What does this circuit do?
The problem can be solved with a simple timing diagram. However, we can explain its action just by inspection. The JK flip?flops are configured as counters (J,K = 1,1 forces the output to toggle on each clock pulse). If JK flipflops are positive?edge triggered and their Q outputs are connected to the clock input of the next stage, they will count down. If we connect the NOT Q outputs to the clocks they will count up. Consequently, we have a binary up counter.
Note the AND gate. This detects Qd,Qc.Qb = 1,1,1. The state of Qa does not matter, so this value will be reached when Qd,Qc.Qb,Qa = 1110 which is 13. When that happens, all flip?flops will be set to zero. This is a modulo 13 counter that counts 0,1,2, …10,11,12, 0, 1, 2 , …
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