Assuming the same systems as question 46, what is the average memory latency for a trip round the loop if prefetching is used and each access to main memory results in the next line being loaded into L2 cache? Assume that preloading the L2 cache incurs no further memory access penalty.
What will be an ideal response?
In this case we have to consider pairs of memory accesses across two trips round the loop.
On the first trip, a memory access takes place, a miss occurs and memory is accessed and L2 updated with the
second line. The access time is as before, 44 cycles.
On the second trip, an access to the array does not miss and the access time for the loop is 6 (L2) + 2 + 2 = 10
cycles. The average memory time per loop is ½ (44 + 10) = 27 cycles.
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