We said (when discussing the potential limitations of VLIW computers) “If a VLIW with m operations per bundle has an instruction with an n?cycle latency, up to m?n ? 1 execution slots are lost.” Demonstrate the truth or otherwise of this statement.
What will be an ideal response?
In the worst case, if only one instruction can be used in a bundle and that instruction has a latency, then the number of instruction slots generated is bundle width × latency cycles. This is m? n. Since there is one instruction in these slots, up to m? n ? 1 slots are lost.
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