A CPU with a 24?bit address bus and 16?bit data bus implements the following memory blocks:

Question

i. 1 M byte of ROM using 256K × 8?bit chips
ii. 8 M bytes of DRAM using 2M × 4?bit chips
Design an address decoder to implement the above arrangement.

Answer 1

i. 1 M byte of ROM using 256K × 8?bit chips
The chips are byte?wide so two are needed to span the bus. This provides 2 × 256K = 512K bytes. As we
need 1 MB, we need two banks (four chips in all).
The 512K byte address space provided by two chips is spanned by address lines A00 to A18. This leaves
address lines A19 to A23 to be decoded. Address line A19 distinguishes between the two banks and address
lines A20 – A23 must be decoded to select this memory block (1 MB of 16 MB).
ii. 8 M bytes of DRAM using 2M × 4?bit chips
In this case the chips are 4 bits wide which means that four of them are needed to span the 16?bit data
bus. This provides a block of 4 MB of memory. As we need 8 Mbytes, two banks are needed.
Address lines A00 to A21 select a location within a bank and address line A22 selects one of two banks. That
leaves A23 to select the upper or lower half of memory space.