A computer has a 256 word memory and a 16 word cache. The cache line size is one word. The following sequence of addresses is read in series:
0,1,2,3,4,5,10,13,16,19,21,4,8,12,30,40,41,42,35,1,3,13
Show how the cache memory would be accessed assuming that all lines are initially invalid. In each cache mark
the access as hit, capacity miss, compulsory miss, conflict miss. Do this for:
a. Fully associative cache
b. Direct mapped cache
c. Two?way set associative cache
a. The following shows the fully?associative mapped cache. A least recently used replacement algorithm is
used when the cache is full.
0,1,2,3,4,5,10,13,16,19,21,4,8,12,30,40,41,42,35,1,3,13
b. The following is a direct?mapped cache.
When the addresses are applied to a 16 line cache, they are modulo 16. The original addresses are:
0,1,2,3,4,5,10,13,16,19,21,4,8,12,30,40,41,42,35,1,3,13. These generate the cache line addresses:
0,1,2,3,4,5,10,13,0,3,5,4,8,12,14,8,9,10,3,1,3,13.
c. The following is a two?way set?associative cache. There are two 8?line caches.
When the addresses are applied to an 8?line cache, they are modulo 8. The original addresses are: 0,1,2,3,
4,5,10,13, 16,19,21,4, 8,12,30,40, 41,42,35,1, 3,13. These generate the cache line addresses: 0,1,2,3,
4,5,2,5, 0,3,5,4, 0,4,6,0, 1,2,3,1, 3,5. In the table a figure in blue indicates a conflict (the existing line is over
written).
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