Describe how the synchronous counter operates.
What will be an ideal response?
A synchronous counter operates as follows. Initially the counter is reset with both flip-flops in the 0 state. When the first clock pulse is applied, the first flip-flop toggles and the output goes high. The second flip-flop does not toggle because of the delay from the input to the actual changing of the output state. Therefore, there is no change in the second flip-flop output state. When the second clock pulse is applied, the first flip-flop toggles and the output goes low. Because there is a high from the output of the first stage, the second stage toggles and its output goes high. After four clock pulses, the counter recycles to its original state.
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What will be an ideal response?
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