A RISC processor has a three?address instruction format and typical arithmetic instructions (i.e., ADD, SUB, MUL, DIV etc.). Write a suitable sequence of instructions to evaluate the following expression in the minimum time:
What will be an ideal response?
Assume that all variables are in registers and that the RISC does not include a hardware mechanism for the
elimination of data dependency. Each instance of data dependency causes one bubble in the pipeline and wastes
one clock cycle.
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