Suppose you could include cache memory in DRAM chips. How would you organize it and what would the advantages be? What changes might have to be made to the computer system architecture?
What will be an ideal response?
There are many possible answers. It all depends on the relative size of the DRAM and the cache. In the limit (very large DRAM) the cache could, effectively, be a form of L3 or L4 cache. DRAMs are often organized to operate on a burst mode (a group of sequential addresses). Any on?board cache would have to take account
of that. Moreover, the external interface would also have to take account of the cache by providing a much faster data exchange when the DRAM’s cache was accessed; that is, the bus would have to be capable of operating at either DRAM speed (internal DRAM cache miss) or the speed of the DRAM’s cache (internal
DRAM cache hit). It would also be necessary for the cache within the DRAM to be updated automatically and invisibly following a miss to the cache).
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