A RISC processor executes the following code. There are data dependencies but no internal forwarding. A source operand cannot be used until it has been written.
ADD r0,r1,r2
ADD r3,r0,r4
ADD r5,r3,r6
ADD r7,r0,r8
ADD r9,r0,r3
ADD r0,r1,r3
a. Assuming a 4?stage pipeline: fetch, operand fetch, execute, result write, what registers are being read during
the 10th clock cycle and what register is being written?
b. How long will it take to execute the entire sequence?
a. In the 10th cycle registers r0 and r3 are being read and register r5 is being written.
b. It takes 13 cycles to complete the sequence.
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