A peripheral interface chip may have several internal registers. Explain the techniques available to reduce the number of address lines required to access these registers. Can you think of any techniques (not discussed in this text) that could be used to allow n address lines to select more than 2n registers?

Question

What will be an ideal response?

Answer 1

If a computer connects n address lines to a memory device, up to 2n locations are uniquely addressable. Although less important today when chips can have very many pins, peripheral manufacturers once attempted to reduce the pin?count by cutting down the number of address lines (to allow the remaining pins to be used for the actual I/O operation rather than the CPU interface). One simple technique is to save one pin by using the R/W* (read/NotWrite) line as an address input to the peripheral. This divides the address space into two, read?only and write?only. This technique is often acceptable for I/O transfers, because data?in and data?out registers can easily be separated (i.e., they are mutually exclusive, because you never write to an input register or read an output register). Equally, system registers are usually read?only (status information) or write?only (control information).

Another way of reducing address pins is to use control bits in a register as a pointer to other registers. For example, you could have two registers: pointer and control/data that require only one address line to distinguish between them. You first load a register value into the pointer register and then you access the corresponding data register. The data register you access depends on the value of the pointer.

Because registers in a peripheral are often accessed in order, you could implement auto?addressing. After a reset, register 0 is accessed. If you access the same peripheral port again, then the next access will be to register 1, and so on. This technique requires an on?chip counter in the peripheral that is incremented after each register access.

One possible way of reducing the number of address lines would be to include a look up table within the peripheral (a form of memory management). This assumes that you have p registers but access only q of them, where q < p. Suppose you have two address lines and 16 registers. The two address lines can access four pointers in a table and each pointer points to one of the 16 registers. Thus, you can access all 16 registers, but only four of them at a time. If you wish to access other registers, the register pointer table has to be reloaded