For the circuit shown in Figure P5.41, assume that switch S2 is always held open and that switch S1 is closed until being opened at t = 0. Subsequently, S1 closes at t = 3? and remains closed. Also assume DC steady-state conditions for t < 0 and
R1 = 5?, R2 = 4?, R3 = 3?, R4 = 6?, and
C1 = C2 = 4F.
a. Find the capacitor voltage vC at t = 0+.
b. Find vC for 0 < t < 3? .
c. Use part b to find the capacitor voltage vC at t = 3? , and use it to find vC for t > 3? .
d. Compare the two time constants for 0 < t < 3? and t > 3? .
e. Sketch vC for all time.
Analysis:
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