If you have an m?bit register, loading an m?bit constant presents a bit of a problem. Discuss how ISA designers have gone about solving this problem in both CISC and RISC domains.

Question

What will be an ideal response?

Answer 1

This is one of the problems of ISA design – dealing with literals and pointers. If instructions were more than 100
bits long, you could have 64?bit literals and that would satisfy most users for most of the time. But, in the real
world, there’s a problem. CISC style processors solved the problem with multilength instructions. If you have an
8?bit processor with 8?bit instructions, you add an 8?bit constant by appending a second word and a 16?bit
constant by appending two 8?bit words. Variable length instructions solve the problems of constants neatly.
RISC processors have constant size instructions. They attempt to embed constants; for example, MIPS has an 11
bit literal field and that can be fitted within the 32?bit instruction. Because only one operand is needed in a
literal operation like addi $1,$2,1234 , the unused 5?bit address field of the third operand is concatenated
with the literal field to create a 5 + 11 = 16 bit literal. That’s nice because it’s half a word and you can therefore
load a 32 bit literal value with two instructions. To do this, MIPS has a lui (load upper word immediate)
instruction that can load a 16?bit value into the upper order word of a register.

ARM processors use pseudo instructions to load literals. They store literals in a pool in memory (near to the
code) and then use a program counter relative load to pick up the literal.