ARM processors perform predicated operations; for example ADDEQ performs an addition only if the Z?bit is set. Multimedia instructions that operate with multiple independent words don’t set the condition code bits; for example, Intel’s comparisons are used to set subwords to all 0s or all 1s that can be later used as masks in logical operations. Suppose you were proposing to add something like the MMX extensions to an ARM?like instruction set with a three or four register instruction format, how do you think you could take advantage of predicated execution?

Question

What will be an ideal response?

Answer 1

If you are using a three register format, you could compare two registers to create a mask register (nondestructively).
The ARM processor’s normal predication mechanism could be used to decide the nature of the
comparison; for example equal, not equal, greater than, and less than. For example,
If r0 = 0x12345678 and r1 = 0x12AB56DC, then the hypothetical parallel compare bytes for equality operation
PCMPBEQ r2,r0,r1 would load r2 with 0xFF00FF00.
A three?register format could be used to support operations like MAXb r0,r1,r2 where r0 contains the
maximum of each pair of bytes in r1 and r2.
However, if you have a four register format, you could implement an operation like MASK r0,r1,r2,r3
where the word in [r0] =[r1] if [r3 ==0] else [r2] (perform this for each subword). This would allow you to
perform the chroma key operation with one instruction where r0 is the output, r1 and r2 are the two images to
mix, and r3 contains the blue mask.
The ARM’s predicated instructions applied to packed multimedia operations would provide greater flexibility
than the MMX’s unpredicated execution mechanism. However, predication cannot always be easily applied to
multimedia operations because the predication is on a single bit (e.g., zero or carry) and applies to the whole
instruction. However, multimedia values are bundles of words in a single register which means that predication
may not always be suitable.