Consider a computer with a 256?byte address space and a two?way set associative cache. The computer word size is a byte, each cache line contains four bytes, and each cache four lines. If the cache is initially empty and the following sequence of hexadecimal addresses is read, show the corresponding sequence of hits and misses.
Address sequence: 48, 0C, 48, 4C, 5C, 3A, 20, 21, 22, 24, 81, 49, 30, 34, 27, 3E, 24, 28, 2C, 40
There are 4 bytes/line so two address bits A0 and A1 select a byte. A set has 4 lines so two address bits A2 and A3
select a line. Bits A4 to A7 select a set. Because the cache is 2?way set associative, two lines with the same
number can be cached simultaneously. We will call the sets A and B.
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