The x86-64 architecture uses four levels of page tables; each level contains 512 entries (using 64-bit PTEs).However, the kernel provides only three levels of page tables.Assuming that each PTE points to a 4KB page, what is the largest address space the kernel can allocate to processes in this architecture?
What will be an ideal response?
The maximum virtual address space size is the number of PTEs per address space
times the size of a page. The number of PTEs per address space is (number of entries per
level)number of levels, which is 5123, or 227. Each page is 4KB, which is 212 bytes. Therefore the
maximum size of a virtual address space is 239 bytes, or 512GB.
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