A computer with a separate data cache has a write?back cache memory. Cache line size is 64 bytes. Read accesses account for 80% of memory traffic. The processor, memory, and data buses are all 64 bits wide. Main memory latency (first access) is 20 cycles and successive accesses take 2 cycles. The cache hit rate is 96%.
Calculate the cost of a cache miss.
On a cache miss a line has to be retrieved from memory. Data is transferred 8 bytes at a time across the 64?bit
bus. The first 8 bytes take 20 cycles. That leaves 64 ? 8 = 56 bytes to transfer across the bus; that is, 56/8 = 7
transfers of 7 × 2 = 14 cycles. Total transfer time = 20 + 14 = 34 cycles.
On a write miss, a cache line has to be updated.
On a read miss the old cache line has to be written back to memory and a new line loaded.
That is: Write miss time 20% × 34 cycles = 6.8 cycles
Read miss access time 2 × 80% × 34 cycles = 54.4 cycles
Total miss access time = 6.8 + 54.4 = 61.2 cycles.
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