A processor with memory management has a 4K page size. It has a 32K cache memory with 16?byte cache lines. In order to speed up memory access, you decide to arrange the cache so that the cache is accessed at the same time a logical to physical address translation is taking place. In order for the scheme to work, what level of associativity must be implemented?
What will be an ideal response?
The cache must look like a memory page to the computer; that is, it must be spanned by address bits A00 to A11
(i.e., 4K). The memory is actually 8 x 4K = 32K which corresponds to an associativity of 8.
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(A) Wapplication followed by a number. (B) Application followed by a number. (C) WindowsApplication. (D) WindowsApplication followed by a number.
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