Why does register renaming prevent write?after?write hazards (WAW) but not read?after?write (RAW) hazards?
What will be an ideal response?
Because a read?after?write hazard is a problem of data dependency that cannot be removed or resolved in any
other way than the correct ordering of instruction execution (unless speculation is used to guess a result before
it is generated). If you have A = B + C followed by E = A + F, you have to execute these instructions serially. A
must first be written and then A must be read. In pipelined processors you can avoid the hazard by forwarding
A from the first operation to the next. In a superscalar processor the instructions cannot be executed in parallel
(or reverse order).
However, a write?after?write dependency is a false dependency because it is apparent. If you have A = B + C, A =
G + H, the two values of A are different variables and therefore there is no dependency. Superscalars solve the
problem by renaming variables (registers) so that the code may become A = B + C, AA = G + H. Now both
instructions can be executed in parallel or reverse order.
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