The clocked circuit below is an arbiter. Suppose two devices 1 and 2 can request a resource such as a bus at any instant. The problem is to ensure that only one requester is granted the resource, even if both requests are made simultaneously. The circuit of Figure P12.20 has two request inputs plus a clock and two grant outputs. Explain how the circuit is able to perform its function reliably. Note that the circuit uses edge?triggered flip?flops and that it is immune to metastablilty.

Question

Answer 1

The following figure provides a timing diagram for the case in which both processors request the bus simultaneously. Request_2 wins and Request_1 must wait until Request_2 has relinquished the bus. That is, Request_1 does not have to try again; it simply waits for the memory to become free.

Initially, the arbiter is idle with both request inputs inactive?high. Therefore, both D inputs to latches 1a and 2a are high, and in a steady state condition. Outputs AA, BB, Grant_1* and Grant_2* are all high.

Suppose that Request_1* and Request_2* are asserted almost simultaneously when the clock is in a high state. This results in the outputs of both OR gates (A and B) going low simultaneously. The cross?coupled feedback inputs to the OR gates (Grant_1* and Grant_2*) are currently both low.

On the next rising edge of the clock, the Q output of latch 1a (i.e. AA) and the Q output of latch 2a (i.e. BB) both go low. However, as latch 2a sees a rising edge clock first, its Q output goes low one half a clock cycle before latch 1's output also goes low.

When a latch is clocked at the moment its input is changing, it may enter a metastable state before the output of the latch settles into one state or the other. For this reason a second pair of latches is used to sample the input latches after the longest settling time.

One clock cycle after Request_2* has been latched and output BB forced low, the output of latch 2b, Grant_2* goes low. Its complement, Grant_2 is fed back to OR gate 1, forcing input A high. After a clock cycle, AA also goes high. Because Grant_2* is connected to latch 1b's active?low preset input, latch 1b is held in a high state.