Both RISC and CISC processors have registers. Answer the following questions about registers.

Question

a. Is it true that a larger number of registers in any architecture is always better than a smaller number?
b. What limits the number of registers that can be implemented by any ISA?
c. What are the relative advantages and disadvantages of dedicated registers like the IA32 architecture
compared to general purpose registers like ARM and MIPS?
d. If you have an m?bit register select field in an instruction, you can’t have more than 2m registers. There are, in
fact, ways round this restriction. Suggest ways of increasing the number of registers beyond 2m while keeping
an m?bit register select field.

Answer 1

a. In principle yes, as long as you don’t have to pay a price for them. More registers means fewer memory
accesses and that is good. However, if you have to perform a context switch when you run a new task, having
to save a lot of registers may be too time?consuming. Having more registers requires more bits in an
instruction to specify them. If you allocate too many bits to register specification then you have a more
limited instruction set.
b. Today, it’s the number of bits required to specify a register. A processor like the Itanium IA64 with a much
longer instruction word can specify more registers.
c. Having fixed special purpose registers permits more compressed code. For example, if you have a counter
register, any instruction using the counter doesn’t need to specify the register – because that is fixed. The
weakness is that you can’t have two counter registers. Computers that originated in the CISC area like the
IA32 architecture use special?purpose registers, because they were designed when saving bits (reducing
instruction size) was important. Remember that early 8?bit microprocessors had an 8?bit instruction set.
More recent architectures are RISC based and have general?purpose architectures. ARM processors are
unusual in the sense that they have a small general?purpose register set that includes two special?purpose
registers, a link register for return addresses and the program counter itself.
d. Of course, you can’t address more than 2m registers with an m?bit address field. But you can use a set of more
than 2m registers of which only 2m are currently visible. Such a so?called windowing technique has been used
in, for example, the Berkeley RISC and the SPARC processor. Essentially, every time you call a
subroutine/function you get a new set of register windows (these are still numbered r0 t0 r31). However,
each function has its own private registers that cannot be accessed from other functions. There are also
global registers common to all functions and parameter passing registers that are shared with parent and
child functions. Such mechanisms have not proved popular. The problem is that if you deeply nest
subroutines, you end up having to dump registers to memory.