If a serial mode cache is used and a 5% penalty in speedup ratio over the corresponding parallel access cache can be tolerated, what value of the hit ratio is necessary to achieve this? Assume that the main store access time is 30 ns and that the cache access time is 3 ns.
What will be an ideal response?
The serial access time is tc + (1 ? h).tm from the previous question, and the parallel access time is h.tc + (1 ? h)?tm. If
serial access time is 5% slower than parallel access time we have:
tc + (1 ? h).tm = 1.05 × (h.tc + (1 ? h)?tm)
Putting in the memory and cache access times, we get 3 + 30(1 ? h) = 1.05 × (3h + 30(1 ? h) )
33 ? 30h = 3.15h + 31.5 ? 31.5h = 31.5 ? 28.35h
1.5 = 1.65 h. Therefore, h = 1.5/1.65 = 0.91
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