The 68020’s CHK2 and CMP2 instructions are rather nice because they let you compare a register against two bounds in order to perform array subscript checking at run time. Unfortunately, they are expensive, because they require two words to be read from memory (the upper and lower bounds) and that is a time?consuming operation. Can you think of a way of implementing such an instruction without incurring such massive penalties?

Question

What will be an ideal response?

Answer 1

Clearly, putting the limits in main store (memory) is not feasible in a load and store world. Of course, you could
have an instruction check r1,r2,r3 that compares r1 against two limits [r2] and [r3] in memory, but that is
not realistic (because memory accesses are expensive). You could implement check r1,r2,r3 that
compares r1 against the contents of limit registers r2 and r3 (i.e., no memory access). One problem is that two
registers are then tied up as limit registers.

Another possibility would be to include explicit limit registers in the processor’s ISA. You would need special
instructions to load them. If you have 16 pairs of limit registers, you could perform a limit check by an
instruction such as CHECK r1,rL1 that compares the contents of r1 against limit register L1. An interesting
way of using an internal limit register would be to combine limit checking with condition code register updating
so that TST r1,rL1 would test r1 and also perform a limit test. Then you could have a branch such as BOL or
BOH (branch out of range low or branch out of range high).