Most RISC processors do not include a block move instruction. What are the advantages and disadvantages of the ARM’s LDM and STM instructions?
What will be an ideal response?
The goal of classic RISC processors is one cycle per instruction (we will see in chapter 7 that this can be achieved by pipelining but is never actually achieved). Instructions that have multiple components such as stack manipulation (pointer changes and data access) or the movement of multiple registers does not fit into RISC philosophy of simple one?cycle operations. However, omitting block moves from the instruction set does leave a hole in the operational capability since block movement is such a common operation. Consequently, ARM has included this very valuable ISA addition.
The ARM processor’s basic load function is LDR r0,[r1] that loads the data in memory pointed at by r1 into register r2, and this is provided by all RISC processors. The ARM processor’s load multiple registers, LDM, has a more complex format with options for the addressing modes and options for the register list. One form is Here, the option IA (increment after) indicates that the stack pointer is going to be incremented after its use; that is, it is post?incrementing. The register list is specified by {}. In this case the register list specifies registers r3 to r7 inclusive, plus r9.
The LDM and STM instructions make the ARM processor much more like a conventional CISC processor as far as
the stack is concerned.
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