From first principles derive an expression for the speedup ratio of a memory system with cache (assume the hit ratio is h, and the ratio of main store access time to cache access time is k, where k < 1). Assume that the system is an ideal system and that you don't have to worry about the effect of clock cycle times.
What will be an ideal response?
The time to access a memory without cache is n?tm, where n is the number of accesses and tm the memory
access time.
The total time to access memory is the time due to cache accesses plus the time due to main memory accesses,
that is, n?(tc?h + tm?m), where h is the hit rate and m the miss rate.
The speedup ratio is n?tm/(n.(tc?h + tm?m)) = tm/(tc.h + tm?m). However, m = 1 ? h because h + m = 1 (an access is
either a hit or a miss).
Speedup ratio = tm/(tc?h + tm?(1 ? h)) = 1/(h?tc/tm + 1 ? h) = 1/(h?k + 1 ? h) where tc/tm = k.
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